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1 features ? low-voltage and standard-voltage operation ? 2.7 (v cc = 2.7v to 5.5v) ? 1.8 (v cc = 1.8v to 3.6v) internally organized 16 ,384 x 8 and 32,768 x 8 two-wire serial interface schmitt trigger, filtered inputs for noise suppression bidirectional data transfer protocol 1 mhz (5v), 400 khz (2.7v, 2.5v) and 100 khz (1.8v) compatibility write protect pin for hardware and software data protection 64-byte page write mode (partial page writes allowed) self-timed write cycle (5 ms max) high reliability ? endurance: one million write cycles ? data retention: 40 years extended temperature an d lead-free/halogen-free devices available 8-lead jedec pdip, 8-lead je dec and eiaj soic, 8-lead ma p, 8-lead tssop, 8-lead sap and 8-ball dbga2 packages die sales: wafer form, waffle pack, and bumped wafers description the at24c128/256 provides 131,072/262,144 bits of serial electrically erasable and programmable read only memory (eeprom) organized as 16,384/32,768 words of 8 bits each. the device?s casca dable feature allows up to 4 devices to share a common two-wire bus. the device is optimized for use in many industrial and commercial appli- cations where low power and low voltage operation are essential. the devices are available in space-saving 8-lead jedec pdip, 8-lead jedec soic, 8-lead eiaj soic, 8-lead map (24c128), 8-lead tssop, 8-lead soic array package and 8-ball dbga2 packages. in addition, the entire family is available in 2.7v (2.7v to 5.5v) and 1.8v (1.8v to 3.6v) versions. table 1. pin configuration pin name function a0 - a1 address inputs sda serial data scl serial clock input wp write protect nc no connect gnd ground 8-lead sap bottom view 1 2 3 4 8 7 6 5 vcc wp scl sda a0 a1 nc gnd two-wire serial eeproms 128k (16,384 x 8) 256k (32,768 x 8) at24c128 at24c256 (1) note: 1. not recommended for new design; please refer to at24c256b datasheet. 0670s?seepr?5/06 8-lead pdip 1 2 3 4 8 7 6 5 a0 a1 nc gnd vcc wp scl sda 8-lead soic 1 2 3 4 8 7 6 5 a0 a1 nc gnd vcc wp scl sda 8-ball dbga2 bottom view vcc wp scl sda a0 a1 nc gnd 1 2 3 4 8 7 6 5 8-lead tssop 1 2 3 4 8 7 6 5 a0 a1 nc gnd vcc wp scl sda 8-lead map bottom view 1 2 3 4 8 7 6 5 vcc wp scl sda a0 a1 nc gnd
2 at24c128/256 0670s?seepr?5/06 figure 1. block diagram absolute maximum ratings* operating temperature..................................?55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .....................................?65 c to +150 c voltage on any pin with respect to ground .................................... ?1.0v to +7.0v maximum operating voltage .......................................... 6.25v dc output current........................................................ 5.0 ma
3 at24c128/256 0670s?seepr?5/06 pin description serial clock (scl): the scl input is used to positive edge clock data into each eeprom device and negat ive edge clock data out of each device. serial data (sda): the sda pin is bidirectional for serial data transfer. this pin is open- drain driven and may be wire-ored with any number of other open-drain or open collector devices. device/addresses (a1, a0): the a1 and a0 pins are device address inputs that are hard- wired or left not connected fo r hardware compatibility with othe r at24cxx devices. when the pins are hardwired, as many as four 128k /256k devices may be addressed on a single bus system (device addressing is discussed in deta il under the device addressing section). if the pins are left floating, the a1 and a0 pins will be internally pulled down to gnd if the capacitive coupling to the circuit board v cc plane is <3 pf. if coupling is >3 pf, atmel recommends con- necting the address pins to gnd. write protect (wp): the write protect input, when connect ed to gnd, allo ws normal write operations. when wp is connected high to v cc , all write operations to the memory are inhib- ited. if the pin is left floating, the wp pin will be internally pulled dow n to gnd if the capacitive coupling to the circuit board v cc plane is <3 pf. if coupling is >3 pf, atmel recommends con- necting the pin to gnd. memory organization at24c128/256, 128k/256k serial eeprom: the 128k/256k is internally organized as 256/512 pages of 64-bytes each. random word addressing requires a 14/15-bit data word address.
4 at24c128/256 0670s?seepr?5/06 table 2. pin capacitance (1) note: 1. this parameter is characterized and is not 100% tested. table 3. dc characteristics (1) notes: 1. v il min and v ih max are reference only and are not tested. 2. the at24c128/256 bearing the process letter ?b? on the package (the mark is located in the lower right corner on the top- side of the package) are approved for operation in the extended temperature range. applicable over recommended operating range from t a = 25 c, f = 1.0 mhz, v cc = +1.8v. symbol test condition max units conditions c i/o input/output capacitance (sda) 8 pf v i/o = 0v c in input capacitance (a 0 , a 1 , scl) 6 pf v in = 0v applicable over recommended operating range from: t ai = ? 40 c to +85 c, v cc = +1.8v to +5.5v; t ae = ? 40 c to +125 c (2) , v cc = +2.7v to +5.5v(unless otherwise noted). symbol parameter test co ndition min typ max units v cc1 supply voltage 1.8 3.6 v v cc2 supply voltage 2.5 5.5 v v cc3 supply voltage 4.5 5.5 v i cc1 supply current v cc = 5.0v read at 400 khz 1.0 2.0 ma i cc2 supply current v cc = 5.0v write at 400 khz 2.0 3.0 ma i sb1 standby current (1.8v option) v cc = 1.8v v in = v cc or v ss 0.2 a v cc = 3.6v 2.0 i sb2 standby current (2.5v option) v cc = 2.5v v in = v cc or v ss 0.5 a v cc = 5.5v 6.0 i sb3 standby current (5.0v option) v cc = 4.5 - 5.5v v in = v cc or v ss 6.0 a i li input leakage current v in = v cc or v ss 0.10 3.0 a i lo output leakage current v out = v cc or v ss 0.05 3.0 a v il input low level (1) ?0.6 v cc x 0.3 v v ih input high level (1) v cc x 0.7 v cc + 0.5 v v ol2 output low level v cc = 3.0v i ol = 2.1 ma 0.4 v v ol1 output low level v cc = 1.8v i ol = 0.15 ma 0.2 v
5 at24c128/256 0670s?seepr?5/06 table 4. ac characteristics ? industrial temperatures notes: 1. this parameter is characterized and is not 100% tested. 2. ac measurement conditions: r l (connects to v cc ): 1.3 k ? (2.5v, 5v), 10 k ? (1.8v) input pulse voltages: 0.3 v cc to 0.7 v cc input rise and fall times: 50 ns input and output timing reference voltages: 0.5 v cc 3. the write cycle time of 5 ms only applies to the at24c 128/256 devices bearing the process letter ?b? on the package (the mark is located in the lower right corner on the top side of the package). 4. the at24c128/256 bearing the process letter ?b? in the package (the mark is located in the lower right corner on the top side of the package), guarantees 1 millio n write cycle endurance (1.8 ? 3.6v). applicable over recommended operating range from t ai = ? 40 c to +85 c, v cc = +1.8v to +5.5v, cl = 100 pf (unless oth- erwise noted). test conditions are listed in note 2. symbol parameter 1.8-volt 2.5-volt 5.0-volt units min max min max min max f scl clock frequency, scl 100 400 1000 khz t low clock pulse width low 4.7 1.3 0.4 s t high clock pulse width high 4.0 0.6 0.4 s t aa clock low to data out valid 0.1 4.5 0.05 0.9 0.05 0.55 s t buf time the bus must be free before a new transmission can start (1) 4.7 1.3 0.5 s t hd.sta start hold time 4.0 0.6 0.25 s t su.sta start set-up time 4.7 0.6 0.25 s t hd.dat data in hold time 0 0 0 s t su.dat data in set-up time 200 100 100 ns t r inputs rise time (1) 1.0 0.3 0.3 s t f inputs fall time (1) 300 300 100 ns t su.sto stop set-up time 4.7 0.6 0.25 s t dh data out hold time 100 50 50 ns t wr write cycle time 20 or 5 (3) 10 or 5 (3) 10 or 5 (3) ms endurance (1) 25c, page mode 100k or 1,000,000 (4) write cycles
6 at24c128/256 0670s?seepr?5/06 table 5. ac characteristics (5) ? extended temperatures notes: 1. this parameter is characterized and is not 100% tested. 2. ac measurement conditions: r l (connects to v cc ): 1.3 k ? (2.5v, 5v), 10 k ? (1.8v) input pulse voltages: 0.3 v cc to 0.7 v cc input rise and fall times: 50 ns input and output timing reference voltages: 0.5 v cc 3. the write cycle time of 5 ms only applies to the at24c 128/256 devices bearing the process letter ?b? on the package (the mark is located in the lower right corner on the top side of the package). 4. the at24c128/256 bearing the process letter ?b? in the package (the mark is located in the lower right corner on the top side of the package), guarantees 1 millio n write cycle endurance (1.8 ? 3.6v). 5. the at24c128/256 bearing the process letter ?b? on the package (the mark is located in the lo wer right corner on the top- side of the package) are approved for operation in the extended temperature range. applicable over recommended operating range from t ae = ? 40 c to +125 c, v cc = +2.7v to +5.5v, cl = 100 pf (unless otherwise noted). test conditions are listed in note 2. symbol parameter 2.7-volt 5.0-volt units min max min max f scl clock frequency, scl 400 1000 khz t low clock pulse width low 1.3 0.4 s t high clock pulse width high 0.6 0.4 s t aa clock low to data out valid 0.05 0.9 0.05 0.55 s t buf time the bus must be free before a new transmission can start (1) 1.3 0.5 s t hd.sta start hold time 0.6 0.25 s t su.sta start set-up time 0.6 0.25 s t hd.dat data in hold time 0 0 s t su.dat data in set-up time 100 100 ns t r inputs rise time (1) 0.3 0.3 s t f inputs fall time (1) 300 100 ns t su.sto stop set-up time 0.6 0.25 s t dh data out hold time 50 50 ns t wr write cycle time 10 or 5 (3) 10 or 5 (3) ms endurance (1) 25c, page mode 100k or 1,000,000 (4) write cycles
7 at24c128/256 0670s?seepr?5/06 device operation clock and data transitions: the sda pin is normally pulled high with an external device. data on the sda pin may change only during scl low time periods (see figure 4 on page 8). data changes during scl high periods will indica te a start or stop condition as defined below. start condition: a high-to-low transition of sda with scl high is a start condition which must precede any other command (see figure 5 on page 9). stop condition: a low-to-high transition of sda with scl high is a stop condition. after a read sequence, the stop comm and will place the eeprom in a standby power mode (see fig- ure 5 on page 9). acknowledge: all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. the eepr om sends a zero du ring the ninth clock cycle to acknowl- edge that it has received each word. standby mode: the at24c128/256 features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the stop bit and the completion of any internal operations. memory reset: after an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: (a) cloc k up to 9 cycles, (b) look for sda high in each cycle while scl is high and then (c) create a start condition as sda is high.
8 at24c128/256 0670s?seepr?5/06 figure 2. bus timing (scl: serial clock, sda: serial data i/o ? ) figure 3. write cycle timing (scl: serial clock, sda: serial data i/o) note: 1. the write cycle time t wr is the time from a valid stop condition of a write s equence to the end of the internal clear/write cycle. figure 4. data validity t wr (1) stop condition start condition wordn ack 8th bit scl sda
9 at24c128/256 0670s?seepr?5/06 figure 5. start and stop definition figure 6. output acknowledge device addressing the 128k/256k eeprom requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see figure 7 on page 11). the device address word consists of a mandatory one, zero sequence for the first five most significant bits as shown. this is common to all two-wire eeprom devices. the 128k/256k uses the two device address bits a1, a0 to allow as many as four devices on the same bus. these bits must compare to their corresponding hardwired input pins. the a1 and a0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. the eighth bit of the device address is the read/ write operation select bit. a read operation is initiated if this bit is high and a write operation is initiated if this bit is low. upon a compare of the device address, the eeprom will output a zero. if a compare is not made, the device will retu rn to a standby state. data security: the at24c128/256 has a hardware data protection scheme that allows the user to write protect the whole memory when the wp pin is at v cc .
10 at24c128/256 0670s?seepr?5/06 write operations byte write: a write operation requires two 8-bit data word addresses following the device address word and ackn owledgment. upon receipt of this address, the eeprom will again respond with a zero and then clock in the first 8-bit data word. following receipt of the 8-bit data word, the eeprom will outpu t a zero. the addressing device, such as a microcontroller, then must terminat e the write sequ ence with a stop condition. at this time the eeprom enters an internally-timed write cycle, t wr , to the nonvolatile memory. all inputs are disabled during this write cycle and the eeprom will not respond until the write is complete (see figure 8 on page 11). page write: the 128k/256k eeprom is capa ble of 64-byte page writes. a page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first da ta word is clocked in. instea d, after the eeprom acknowledges receipt of the first data word, the microcontroller can transmit up to 63 more data words. the eeprom will respond with a ze ro after each data word receiv ed. the microcontroller must ter- minate the page write sequence with a stop condition (see figure 9 on page 12). the data word address lower 6 bits are internally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. if more than 64 data words are transmitted to the eeprom, the data word addres s will ?roll over? and previous data will be overwritten. the address ?roll over? during write is from the last byte of the current page to the first byte of the same page. acknowledge polling: once the internally-timed write cycle has started and the eeprom inputs are disabled, acknowledge polling c an be initiated. this involves sending a start condition followed by the device address word. the read/write bit is representative of the operation desired. only if t he internal write cycle has co mpleted will the eeprom respond with a zero, allowing the read or write sequence to continue.
11 at24c128/256 0670s?seepr?5/06 read operations read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. there are three read operations: current address read, random address read and sequential read. current address read: the internal data word addr ess counter main tains the last address accessed during the last read or write operation, incremented by one. this address stays valid between operations as long as the chip power is maintained. the address ?roll over? during read is from the last byte of the last memory page, to the first byte of the first page. once the device address with the read/write sele ct bit set to one is clocked in and acknowl- edged by the eeprom, the current address dat a word is serially clocked out. the microcontroller does not respond with an input zero but does generate a following stop condi- tion (see figure 10 on page 12). random read: a random read requires a ?dummy? byte write sequence to load in the data word address. once the device address wo rd and data word address are clocked in and acknowledged by the eeprom, the microcontr oller must generate another start condition. the microcontroller now initiates a current address read by sending a device address with the read/write select bit high. th e eeprom acknowledges the device address and serially clocks out the data word. the microcontroller does not respond with a zero but does generate a fol- lowing stop condition (see figure 11 on page 12). sequential read: sequential reads are initiated by either a current address read or a ran- dom address read. after the microcontroller receives a data word, it responds with an acknowledge. as long as the eepr om receives an ackn owledge, it will cont inue to increment the data word address and serially clock out sequential data words. when the memory address limit is reache d, the data word address will ?roll over? and the sequential read will con- tinue. the sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (see figure 12 on page 12). figure 7. device address figure 8. byte write
12 at24c128/256 0670s?seepr?5/06 figure 9. page write notes: (* = don?t care bit) (? = don?t care bit for the 128k) figure 10. current address read figure 11. random read notes: (* = don?t care bit) (? = don?t care bit for the 128k) figure 12. sequential read
13 at24c128/256 0670s?seepr?5/06 notes: 1. for 2.7v devices used in the 4.5v to 5.5v range, pleas e refer to performance values in the ac and dc characteristics ta bles. 2. ?u? designates green package + rohs compliant. 3. available in waffle pack and wafer form; order as sl719 for wafer form. bumped die available upon request. please contact serial eeprom marketing. at24c128 ordering information (1) ordering code package operation range at24c128-10pi-2.7 at24c128n-10si-2.7 at24c128w-10si-2.7 at24c128-10ti-2.7 8p3 8s1 8s2 8a2 industrial temperature (?40 c to 85 c) at24c128-10pi-1.8 at24c128n-10si-1.8 at24c128w-10si-1.8 at24c128-10ti-1.8 8p3 8s1 8s2 8a2 industrial temperature (?40 c to 85 c) at24c128-10pu-2.7 (2) at24c128-10pu-1.8 (2) at24c128n-10su-2.7 (2) at24c128n-10su-1.8 (2) at24c128w-10su-2.7 (2) at24c128w-10su-1.8 (2) at24c128-10tu-2.7 (2) at24c128-10tu-1.8 (2) at24c128u2-10uu-1.8 (2) at24c128y1-10yu-1.8 (2) at24c128y4-10yu-1.8 (2) 8p3 8p3 8s1 8s1 8s2 8s2 8a2 8a2 8u2-1 8y1 8y4 lead-free/halogen-free/ industrial temperature (?40 c to 85 c) at24c128-w2.7-11 (3) at24c128-w1.8-11 (3) die sale die sale industrial temperature (?40 c to 85 c) package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline package (jedec soic) 8s2 8-lead, 0.200" wide, plastic gull wing small outline package (eiaj soic) 8u2-1 8-ball, die ball grid array package (dbga2) 8y1 8-lead, 4.90 mm x 3.00 mm body, dual footprin t, non-leaded, miniature array package (map) 8y4 8-lead, 6.00 mm x 4.90 mm body, dual footpr int, non-leaded, small array package (sap) 8a2 8-lead, 4.4 mm body, plastic thin shrink small outline package (tssop) options ? 2.7 low-voltage (2.7v to 5.5v) ? 1.8 low-voltage (1.8v to 3.6v)
14 at24c128/256 0670s?seepr?5/06 notes: 1. this device is not recommended for new design. please refer to at24c256b datasheet. for 2.7v devices used in the 4.5v t o 5.5v range, please refer to performance values in the ac and dc characteristics tables. 2. ?u? designates green package + rohs compliant. 3. available in waffle pack and wafer form; order as sl719 for wafer form. bumped die available upon request. please contact serial eeprom marketing. at24c256 ordering information (1) ordering code package operation range at24c256-10pi-2.7 at24c256n-10si-2.7 at24c256w-10si-2.7 at24c256-10ti-2.7 8p3 8s1 8s2 8a2 industrial temperature (?40 c to 85 c) at24c256-10pi-1.8 at24c256n-10si-1.8 at24c256w-10si-1.8 at24c256-10ti-1.8 8p3 8s1 8s2 8a2 industrial temperature (?40 c to 85 c) at24c256-10pu-2.7 (2) at24c256-10pu-1.8 (2) at24c256n-10su-2.7 (2) at24c256n-10su-1.8 (2) at24c256w-10su-2.7 (2) at24c256w-10su-1.8 (2) at24c256-10tu-2.7 (2) at24c256-10tu-1.8 (2) at24c256u2-10uu-1.8 (2) at24c256y1-10yu-1.8 (2) at24c256y4-10yu-1.8 (2) 8p3 8p3 8s1 8s1 8s2 8s2 8a2 8a2 8u2-1 8y1 8y4 lead-free/halogen-free/ industrial temperature (?40 c to 85 c) at24c256-w2.7-11 (3) at24c256-w1.8-11 (3) die sale die sale industrial temperature (?40 c to 85 c) package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline package (jedec soic) 8s2 8-lead, 0.200" wide, plastic gull wing small outline package (eiaj soic) 8u2-1 8-ball, die ball grid array package (dbga2) 8y1 8-lead, 4.90 mm x 3.00 mm body, dual footprin t, non-leaded, miniature array package (map) 8y4 8-lead, 6.00 mm x 4.90 mm body, dual footpr int, non-leaded, small array package (sap) 8a2 8-lead, 4.4 mm body, plastic thin shrink small outline package (tssop) options ? 2.7 low-voltage (2.7v to 5.5v) ? 1.8 low-voltage (1.8v to 3.6v)
15 at24c128/256 0670s?seepr?5/06 packaging information 8p3 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8p3 , 8-lead, 0.300" wide body, plastic dual in-line package (pdip) 01/09/02 8p3 b d d1 e e1 e l b2 b a2 a 1 n ea c b3 4 plcs top view side view end view common dimensions (unit of measure = inches) symbol min nom max note notes: 1. this drawing is for general information only; refer to jedec drawing ms-001, variation ba for additional information. 2. dimensions a and l are measured with the package seated in jedec seating plane gauge gs-3. 3. d, d1 and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0.25 mm). a 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc ea 0.300 bsc 4 l 0.115 0.130 0.150 2
16 at24c128/256 0670s?seepr?5/06 8s1 ? jedec soic 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. note: 10/7/03 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 b common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.00 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? 0? ? 8? ? top view end view side view e b d a a1 n e 1 c e1 l
17 at24c128/256 0670s?seepr?5/06 8s2 ? eiaj soic 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8s2 , 8-lead, 0.209" body, plastic small outline package (eiaj) 10/7/03 8s2 c common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this drawing is for general information only; refer to eiaj drawing edr-7320 for additional information. 2. mismatch of the upper and lower dies and resin burrs are not included. 3. it is recommended that upper and lower cavities be equal. if they are different, the larger dimension shall be regarded. 4. determines the true geometric position. 5. values b and c apply to pb/sn solder plated terminal. the standard thickness of the solder layer shall be 0.010 +0.010/ ? 0.005 mm. a 1.70 2.16 a1 0.05 0.25 b 0.35 0.48 5 c 0.15 0.35 5 d 5.13 5.35 e1 5.18 5.40 2, 3 e 7.70 8.26 l 0.51 0.85 ? 0? 8? e 1.27 bsc 4 end view side view e b a a1 d e n 1 c e1 ? l top view
18 at24c128/256 0670s?seepr?5/06 8u2-1 ? dbga2 1150 e. cheyenne mtn. blvd. color a do s pring s , co 8 0906 title drawing no. r rev. po 8 u2-1 a 6/24/0 3 common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note 8 u2-1, 8 - ba ll, 2. 3 5 x 3 .7 3 mm body, 0.75 mm pitch, s m a ll die b a ll grid arr a y p a ck a ge (dbga2) a 0. 8 1 0.91 1.00 a1 0.15 0.20 0.25 a2 0.40 0.45 0.50 b 0.25 0. 3 0 0. 3 5 2 d 2. 3 5 b s c e 3 .7 3 b s c e 0.75 b s c e1 0.74 ref d 0.75 b s c d1 0. 8 0 ref 1. thi s dr a wing i s for gener a l inform a tion only. 2. dimen s ion ? b? i s me asu red a t the m a xim u m s older ba ll di a meter. d a s ide view top view bottom view 8 s older b a ll s 1 a b c d 2 (e1) e a1 ball pad corner (d1) 1. b a1 a2 d a1 ball pad corner e
19 at24c128/256 0670s?seepr?5/06 8y1 ? map a ? ? 0.90 a1 0.00 ? 0.05 d 4.70 4.90 5.10 e 2.80 3.00 3.20 d1 0.85 1.00 1.15 e1 0.85 1.00 1.15 b 0.25 0.30 0.35 e 0.65 typ l 0.50 0.60 0.70 pin 1 index area d e a a1 b 8 7 6 e 5 l d1 e1 pin 1 index area 1 2 34 a top view end view bottom view side view 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8y1, 8-lead (4.90 x 3.00 mm body) msop array package (map) y1 c 8y1 2/28/03 common dimensions (unit of measure = mm) symbol min nom max note
20 at24c128/256 0670s?seepr?5/06 8y4 ? sap 1150 e. cheyenne mtn. blvd. color a do s pring s , co 8 0906 title drawing no. r rev. 8 y4 , 8 -le a d (6.00 x 4.90 mm body) s oic arr a y p a ck a ge ( s ap) y4 a 8 y4 5/24/04 common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note a ? ? 0.90 a1 0.00 ? 0.05 d 5. 8 0 6.00 6.20 e 4.70 4.90 5.10 d1 2. 8 5 3 .00 3 .15 e1 2. 8 5 3 .00 3 .15 b 0. 3 5 0.40 0.45 e 1.27 typ e1 3 . 8 1 ref l 0.50 0.60 0.70 a e a1 b pin 1 index area d a pin 1 id e1 d1 l e e1
21 at24c128/256 0670s?seepr?5/06 8a2 ? tssop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 5/30/02 common dimensions (unit of measure = mm) symbol min nom max note d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 a ? ? 1.20 a2 0.80 1.00 1.05 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref 8a2 , 8-lead, 4.4 mm body, plastic thin shrink small outline package (tssop) notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, tolerances, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07 mm. 5. dimension d and e1 to be determined at datum plane h. 8a2 b side view end view top view a2 a l l1 d 1 2 3 e1 n b pin 1 indicator this corner e e
22 at24c128/256 0670s?seepr?5/06 revision history doc. rev. comments 0670s implemented revision history page; added note 1 ?not recommended for new design; please refer to at24c256b datasheet? to at24c256 part on pages 1 and 14.
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